ICS842S104CG REVISION A MARCH 17, 2010

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©2010 Integrated Device Technology, Inc.

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer, a

Interface, various device functions, such as individual clock output

buffers, can be individually enabled or disabled. The registers

associated with the serial interface initialize to their default setting

upon power-up, and therefore, use of this interface is optional. Clock

device register changes are normally made upon system

initialization, if any are required.

Data Protocol

The clock driver serial protocol accepts byte write, byte read, block

write and block read operations from the controller. For block

write/read operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the ability to

stop after any complete byte has been transferred. For byte write and

byte read operations, the system controller can access individually

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 3A.

The block write and block read protocol is outlined in Table 3B, while

Table 3C outlines the corresponding byte write and byte read

protocol. The slave receiver address is 11010010 (D2h).

Table 3A.Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation.

6:5

Chip select address, set to “00” to access device.

4:0

Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.