AS3525 datasheet(61/194 Pages) AMSCO

61 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

The following table shows the valid combinations for sdata_source (bit 7 and 6) and i2s_clk_source (bit 9 and 8) of the I2SIN_CONTROL register.

sdata_source

i2s_clk_source

Description

default mode (AFE with AS3525)

external data, external clock

external data, internal clock

data and clock from SPDIF converter

loopback, internal data and clock

Table 44 I2S Input mask register

Name

Base

Default

I2SIN_MASK

AS3525_I2SIN_BASE

0x00

Interrupt mask register

Offset: 0x0004

The interrupt mask register determines which status flags generate an interrupt by

setting the corresponding bit to 1.

Bit

Bit Name

Default

Access

Bit Description

reserved

R/W

stereo24_status cannot assert interrupt request

I2SIN_MASK_PUER

R/W

1 enables the FIFO PUSH error interrupt

I2SIN_MASK_POE

R/W

1 enables the FIFO POP is empty interrupt

I2SIN_MASK_POAE

R/W

1 enables the FIFO POP is almost empty interrupt

I2SIN_MASK_POHF

R/W

1 enables the FIFO POP is half full interrupt

I2SIN_MASK_POAF

R/W

1 enables the FIFO POP is almost full interrupt

I2SIN_MASK_POF

R/W

1 enables the FIFO POP is full interrupt

I2SIN_MASK_POER

R/W

1 enables the FIFO POP error interrupt

Table 45 I2S Input raw status register

Name

Base

Default

I2SIN_RAW_STATUS

AS3525_I2SIN_BASE

0x00

Raw status register

Offset: 0x0008

The read-only raw status register contains the actual bit values as reflected by the

FIFO controller status signals. I2SIN_PUER and I2SIN_POER are static bits, since

FIFO controller gives the PUSH/POP error bit only for one clock. This means that

these two bits remain asserted until they are cleared in the I2SIN_CLEAR register.

All other bits change state depending on the underlying logic, i.e. state of FIFO

controller.

Bit

Bit Name

Default

Access

Bit Description

stereo24_status

Status of write interface for 24 bit stereo mode

0: left audio sample will be transferred next

1: right audio sample will be transferred next

I2SIN_PUER

1 if FIFO PUSH error

I2SIN_POE

1 if FIFO POP is empty

I2SIN_POAE

1 if FIFO POP is almost empty

I2SIN_POHF

1 if FIFO POP is half full

I2SIN_POAF

1 if FIFO POP is almost full

I2SIN_POF

1 if FIFO POP is full

I2SIN_POER

1 if FIFO POP error

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