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AS3525 bảng dữ liệu(PDF) 161 Page - ams AG |
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AS3525 bảng dữ liệu(HTML) 161 Page - ams AG |
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161 / 194 page ![]() AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 161 - 194 Name Base Default IRQ_ENRD_2 I2C audio master 0x00 Third Interrupt Register Offset: 0x27 Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Bit Bit Name Default Access Bit Description x R RTC timer interrupt reading 0: not RTC interrupt occurred 1: RTC timer interrupt occurred.Selecting minute or second interrupt can be done via RTCT register (0x29) 0 W ADC end of conversion interrupt setting 0: disable 1: enable 0 ADC_EndCon (edge) x R ADC end of conversion interrupt reading 0: ADC conversion not finished 1: ADC conversion finished. Read out ADC_0 and ADC_1 register to get the result (0x2E & 0x2F) |
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