AS3525 datasheet(144/194 Pages) AMSCO

144 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

144

- 194

Figure 56 I2S Timing

7.4.10.4 Power Save Options

The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.

7.4.10.5 Clock Supervision

The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit in the

interrupt register represents the actual state (present or not present) of the LRCK.

7.4.10.6 Parameter

Table 128 Audio Converter Parameter

Symbol

Parameter

Notes

Min

Typ

Max

Unit

programmable gain DAC input

-43.43

1.07

Gain

programmable gain ADC output

-34.5

Gain Step-Size

1.5

Mute Attenuation

120

I2S inputs / outputs

VIL

SCLK, LRCK, SDI (30%DVDD/2)

0.42

VIH

SCLK, LRCK, SDI (70%DVDD/2)

1.02

DVDD

VOL

SDO,IRQ @2mA

0.3

VOH

SDO,IRQ @2mA

2.6

TSCLKH

SCLK clock high time

TSCLKL

SCLK clock low time

TSDSU

Data set-up time

SDI versus rising edge of SCLK

TSDHD

Data hold time

SDI versus rising edge of SCLK

TSDOD

Data Output Delay

SDO versus falling edge of SCLK

TLRSU

Clock set up time

LRCK versus rising edge of SCLK

TLRHD

Clock hold time

LRCK versus rising edge of SCLK

TS1, TS2

Clock separation time

MCLCK rising edge versus LRCK

TJITTER

clock Jitter

LRCK

-20

BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned

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