ATmega1284P datasheet(140/380 Pages) ATMEL

140 / 380 page

140

8059D–AVR–11/09

ATmega1284P

15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

15.1

Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

15.2

Overview

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-12.. For the actual

placement of I/O pins, see ”Pin Configurations” on page 2. CPU accessible I/O Registers, includ-

ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations

are listed in the ”Register Description” on page 153.

The Power Reduction Timer/Counter2 bit, PRTIM2, in ”PRR0 – Power Reduction Register 0” on

page 46 must be written to zero to enable Timer/Counter2 module.

Figure 15-1. 8-bit Timer/Counter Block Diagram

Timer/Counter

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA

TCCRnB

clk

ASSRn

Synchronization Unit

Prescaler

T/C

Oscillator

clk

I/O

clk

ASY

asynchronous mode

select (ASn)

Synchronized Status flags

TOSC1

TOSC2

Status flags

clk

I/O

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