ATmega1284P datasheet(5/380 Pages) ATMEL

5 / 380 page

8059D–AVR–11/09

ATmega1284P

2.2.4

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega1284P as listed on

page 80.

2.2.5

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega1284P as listed on page 83.

2.2.6

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega1284P as listed on

page 86.

2.2.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 327. Shorter pulses are not guaranteed to generate a reset.

2.2.8

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.9

XTAL2

Output from the inverting Oscillator amplifier.

2.2.10

AVCC

AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter-

nally connected to V

CC, even if the ADC is not used. If the ADC is used, it should be connected

to V

CC through a low-pass filter.

2.2.11

AREF

This is the analog reference pin for the Analog-to-digital Converter.

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