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ATmega1284P bảng dữ liệu(PDF) 23 Page - ATMEL Corporation |
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ATmega1284P bảng dữ liệu(HTML) 23 Page - ATMEL Corporation |
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23 / 380 page ![]() 23 8059D–AVR–11/09 ATmega1284P When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 6-2 on page 23 lists the typical programming time for EEPROM access from the CPU. Table 6-2. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time EEPROM write (from CPU) 26,368 3.3 ms |
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