ATmega1284P datasheet(137/380 Pages) ATMEL

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137

8059D–AVR–11/09

ATmega1284P

14.11.9

TIMSK3 – Timer/Counter3 Interrupt Mask Register

• Bit 7:6 – Res: Reserved Bits

These bits are unused bits in the ATmega1284P, and will always read as zero.

• Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 59) is executed when the ICF3 Flag, located in TIFR3, is set.

• Bit 4:3 – Res: Reserved Bits

These bits are unused bits in the ATmega1284P, and will always read as zero.

• Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3B Flag, located in

TIFR3, is set.

• Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3A Flag, located in

TIFR3, is set.

• Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See Section “9.3” on page 53.) is executed when the TOV3 Flag, located in TIFR3, is set.

14.11.10 TIFR1 – Timer/Counter1 Interrupt Flag Register

• Bit 7:6 – Res: Reserved Bits

These bits are unused bits in the ATmega1284P, and will always read as zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-

ter reaches the TOP value.

Bit

(0x71)

–

ICIE3

–

OCIE3B

OCIE3A

TOIE3

TIMSK3

Read/Write

R/W

Initial Value

Bit

76543210

0x16 (0x36)

–

ICF1

–

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

R/W

Initial Value

00000000

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