ATmega1284P datasheet(135/380 Pages) ATMEL

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135

8059D–AVR–11/09

ATmega1284P

A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB bits are always read as zero.

14.11.4

TCNTnH and TCNTnL –Timer/Counter n

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See Section “14.3” on

page 112.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-

pare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock

for all compare units.

14.11.5

OCRnAH and OCRnAL – Output Compare Register n A

14.11.6

OCRnBH and OCRnBL – Output Compare Register nB

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See Section “14.3” on page 112.

Bit

76543210

TCNTn[15:8]

TCNTnH

TCNTn[7:0]

TCNTnL

Read/Write

R/W

Initial Value

00000000

Bit

76543210

OCRnA[15:8]

OCRnAH

OCRnA[7:0]

OCRnAL

Read/Write

R/W

Initial Value

00000000

Bit

76543210

OCRnB[15:8]

OCRnBH

OCRnB[7:0]

OCRnBL

Read/Write

R/W

Initial Value

00000000

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