ATmega1284P datasheet(142/380 Pages) ATMEL

142 / 380 page

142

8059D–AVR–11/09

ATmega1284P

15.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

15-2 shows a block diagram of the counter and its surrounding environment.

Figure 15-2. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT2 by 1.

direction

Selects between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T2 in the following.

top

Signalizes that TCNT2 has reached maximum value.

bottom

Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

T2). clkT2 can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk

T2 is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see ”Modes of

Operation” on page 145.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

15.5

Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a

match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical

one to its I/O bit location. The Waveform Generator uses the match signal to generate an output

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

top

bottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

clk

ATmega1284P bảng dữ liệu(PDF) 142 Page - ATMEL Corporation

ATmega1284P bảng dữ liệu(HTML) 142 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL