IMX35 datasheet(32/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and

Table 28 lists the timing parameters.

Figure 10. Trace Data Timing Diagram

4.9.4.1

Half-Rate Clocking Mode

When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and

falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10.

The same Ts and Th parameters from Table 28 still apply with respect to the falling edge of the

TRACECLK signal.

4.9.5

EMI Electrical Specifications

This section provides electrical parametrics and timing for the EMI module.

4.9.5.1

NAND Flash Controller Interface (NFC)

The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and

WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12,

Table 27. ETM TRACECLK Timing Parameters

Parameter

Min.

Max.

Unit

Tcyc

Clock period

Frequency dependent

—

Twl

Low pulse width

—

Twh

High pulse width

—

Clock and data rise time

—

Clock and data fall time

—

Table 28. ETM Trace Data Timing Parameters

Parameter

Min.

Max.

Unit

Data setup

—

Data hold

—

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