DS3106 datasheet(5/87 Pages) MAXIM

5 / 87 page

____________________________________________________________________________________________ DS3106

19-4629; Rev 3; 5/09

5 of 87

List of Tables

Table 1-1. Applicable Telecom Standards................................................................................................................... 6

Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 10

Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 10

Table 6-3. Global Pin Descriptions ............................................................................................................................ 11

Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 12

Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 12

Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 13

Table 7-1. Input Clock Capabilities ............................................................................................................................ 15

Table 7-2. Input Clock Default Frequency Configuration........................................................................................... 15

Table 7-3. Locking Frequency Modes ....................................................................................................................... 15

Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 22

Table 7-5. Output Clock Capabilities ......................................................................................................................... 24

Table 7-6. Digital1 Frequencies................................................................................................................................. 26

Table 7-7. Digital2 Frequencies................................................................................................................................. 26

Table 7-8. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 27

Table 7-9. T0 APLL Frequency Configuration ........................................................................................................... 27

Table 7-10. T0 APLL2 Frequency Configuration ....................................................................................................... 27

Table 7-11. T4 APLL Frequency Configuration ......................................................................................................... 28

Table 7-12. OC3 and OC6 Output Frequency Selection........................................................................................... 28

Table 7-13. Standard Frequencies for Programmable Outputs ................................................................................ 29

Table 7-14. T0FREQ Default Settings....................................................................................................................... 31

Table 7-15. T4FREQ Default Settings....................................................................................................................... 31

Table 7-16. OC6 Default Frequency Configuration ................................................................................................... 31

Table 7-17. OC3 Default Frequency Configuration ................................................................................................... 32

Table 8-1. Register Map ............................................................................................................................................ 38

Table 9-1. JTAG Instruction Codes ........................................................................................................................... 73

Table 9-2. JTAG ID Code .......................................................................................................................................... 74

Table 10-1. Recommended DC Operating Conditions.............................................................................................. 75

Table 10-2. DC Characteristics.................................................................................................................................. 75

Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 76

Table 10-4. LVDS Output Pins .................................................................................................................................. 76

Table 10-5. LVPECL Level-Compatible Output Pins................................................................................................. 77

Table 10-6. Input Clock Timing.................................................................................................................................. 78

Table 10-7. Input Clock to Output Clock Delay ......................................................................................................... 78

Table 10-8. Output Clock Phase Alignment, Frame-Sync Alignment Mode.............................................................. 78

Table 10-9. SPI Interface Timing ............................................................................................................................... 79

Table 10-10. JTAG Interface Timing.......................................................................................................................... 81

Table 10-11. Reset Pin Timing .................................................................................................................................. 82

Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................... 83

Table 13-1. LQFP Package Thermal Properties, Natural Convection....................................................................... 85

Table 13-2. LQFP Theta-JA (

JA) vs. Airflow ............................................................................................................. 85

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