DS3106 datasheet(4/87 Pages) MAXIM

4 / 87 page

____________________________________________________________________________________________ DS3106

19-4629; Rev 3; 5/09

4 of 87

List of Figures

Figure 2-1. Typical Application Example ..................................................................................................................... 7

Figure 3-1. Block Diagram ........................................................................................................................................... 7

Figure 7-1. DPLL Block Diagram ............................................................................................................................... 18

Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 20

Figure 7-3. FSYNC 8kHz Options.............................................................................................................................. 32

Figure 7-4. SPI Clock Phase Options........................................................................................................................ 35

Figure 7-5. SPI Bus Transactions.............................................................................................................................. 35

Figure 9-1. JTAG Block Diagram............................................................................................................................... 70

Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 72

Figure 10-1. Recommended Termination for LVDS Output Pins .............................................................................. 77

Figure 10-2. Recommended Termination for LVPECL-Compatible Output Pins ...................................................... 77

Figure 10-3. SPI Interface Timing Diagram ............................................................................................................... 80

Figure 10-4. JTAG Timing Diagram........................................................................................................................... 81

Figure 10-5. Reset Pin Timing Diagram .................................................................................................................... 82

Figure 11-1. Pin Assignment Diagram....................................................................................................................... 84

DS3106 bảng dữ liệu(PDF) 4 Page - Maxim Integrated Products

DS3106 bảng dữ liệu(HTML) 4 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

bảng dữ liệu tải về

Link URL