DS3106 datasheet(2/87 Pages) MAXIM

2 / 87 page

____________________________________________________________________________________________ DS3106

19-4629; Rev 3; 5/09

2 of 87

Table of Contents

STANDARDS COMPLIANCE ..........................................................................................................6

APPLICATION EXAMPLE ...............................................................................................................7

BLOCK DIAGRAM...........................................................................................................................7

DETAILED DESCRIPTION ..............................................................................................................8

DETAILED FEATURES ...................................................................................................................9

5.1

INPUT CLOCK FEATURES .................................................................................................................9

5.2

DPLL FEATURES.............................................................................................................................9

5.3

OUTPUT APLL FEATURES ...............................................................................................................9

5.4

OUTPUT CLOCK FEATURES..............................................................................................................9

5.5

GENERAL FEATURES .......................................................................................................................9

PIN DESCRIPTIONS......................................................................................................................10

FUNCTIONAL DESCRIPTION .......................................................................................................14

7.1

OVERVIEW ....................................................................................................................................14

7.2

DEVICE IDENTIFICATION AND PROTECTION .....................................................................................14

7.3

LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION.............................................................14

7.4

INPUT CLOCK CONFIGURATION ......................................................................................................15

7.4.1

Signal Format Configuration ................................................................................................................ 15

7.4.2

Frequency Configuration...................................................................................................................... 15

7.5

INPUT CLOCK MONITORING............................................................................................................16

7.5.1

Frequency Monitoring .......................................................................................................................... 16

7.5.2

Activity Monitoring ................................................................................................................................ 16

7.5.3

Selected Reference Activity Monitoring ............................................................................................... 17

7.6

INPUT CLOCK PRIORITY AND SWITCHING........................................................................................17

7.7

DPLL ARCHITECTURE AND CONFIGURATION ..................................................................................18

7.7.1

T0 DPLL State Machine ....................................................................................................................... 19

7.7.2

Bandwidth ............................................................................................................................................ 22

7.7.3

Damping Factor.................................................................................................................................... 22

7.7.4

Phase Detectors................................................................................................................................... 22

7.7.5

Loss-of-Lock Detection ........................................................................................................................ 23

7.7.6

Frequency and Phase Measurement................................................................................................... 24

7.7.7

Input Jitter Tolerance ........................................................................................................................... 24

7.7.8

Jitter Transfer ....................................................................................................................................... 24

7.7.9

Output Jitter and Wander ..................................................................................................................... 24

7.8

OUTPUT CLOCK CONFIGURATION...................................................................................................24

7.8.1

Signal Format Configuration ................................................................................................................ 25

7.8.2

Frequency Configuration...................................................................................................................... 25

7.9

MICROPROCESSOR INTERFACE......................................................................................................33

7.10

RESET LOGIC.............................................................................................................................36

7.11

POWER-SUPPLY CONSIDERATIONS.............................................................................................36

7.12

INITIALIZATION............................................................................................................................36

REGISTER DESCRIPTIONS .........................................................................................................37

8.1

STATUS BITS.................................................................................................................................37

8.2

CONFIGURATION FIELDS................................................................................................................37

8.3

MULTIREGISTER FIELDS.................................................................................................................37

8.4

REGISTER DEFINITIONS .................................................................................................................38

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