DS3106 datasheet(9/87 Pages) MAXIM

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____________________________________________________________________________________________ DS3106

19-4629; Rev 3; 5/09

9 of 87

5. Detailed Features

5.1

Input Clock Features



Two programmable-frequency CMOS/TTL input clocks



Input clocks accept any multiple of 2kHz up to 125MHz



All input clocks are constantly monitored by programmable activity monitors

5.2

DPLL Features



High-resolution DPLL plus three low-jitter output APLLs



Sophisticated state machine automatically transitions between free-run, locked, and holdover states



Programmable bandwidth from 18Hz to 400Hz



Separately configurable acquisition bandwidth and locked bandwidth



Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20



Multiple phase detectors: phase/frequency, early/late, and multicycle



Phase/frequency locking (

360 capture) or nearest edge phase locking (180 capture)



Multicycle phase detection and locking (up to

8191UI) improves jitter tolerance and lock time



High-resolution frequency and phase measurement



Holdover frequency averaging over 1 second interval



Fast detection of input clock failure and transition to holdover mode



Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks

5.3

Output APLL Features



Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates,

Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock



The T0 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x 25MHz, and

N x 62.5MHz



The T4 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3,

N x 10MHz, N x 10.24MHz, N x 13MHz, N x 25MHz, and N x 62.5MHz



The T0 APLL2 produces 312.5MHz for 10G Synchronous Ethernet applications

5.4

Output Clock Features



Two output clocks: one CMOS/TTL (≤ 125MHz) and one LVDS/LVPECL (≤ 312.50MHz)



Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz,

51.84MHz, 77.76MHz, 155.52MHz, 311.04MHz, 2.5MHz, 25MHz, 125MHz, 156.25MHz, 312.50MHz,

10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates



Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz,

and any multiple of 10kHz up to 388.79MHz



All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak



8kHz frame-sync and 2kHz multiframe-sync outputs have programmable polarity and pulse width, and can

be disciplined by a 2kHz or 8kHz sync input

5.5

General Features



Operates from a single external 12.800MHz local oscillator (XO or TCXO)



SPI serial microprocessor interface



Four general-purpose I/O pins



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