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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PCM5310PAPR bảng dữ liệu(PDF) 78 Page - Texas Instruments |
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PCM5310PAPR bảng dữ liệu(HTML) 78 Page - Texas Instruments |
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78 / 103 page  Register 104 (68h) LRCK4 BCK4 LRCK1 BCK1 LRCK2 BCK2 LRCK3 BCK3 LRCK,BCKfromADC12atMaster LRCK,BCKfromADC34atMaster LRCK,BCKfromDAC12atMaster DATAfromGPIO1 DATAfromADC12 LRCK,BCKfromDAC34atMaster DATAfromGPIO2 DATAfromADC34 SCK4 SCK1 SCK2 SCK3 DATA4 DATA1 DATA2 DATA3 LRCK/BCKtoMUX_ADCxxandMUXDACxx SCKtoMUX_ADCxxandMUXDACxx DATAtoMUXDACxx LRCK5 BCK5 LRCK6 BCK6 SCK5 SCK6 DATA5 DATA6 Register105 DTS4[3:0] Register106 SCS1[2:0] Register104 LBS4[3:0] PORT-4 PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 104 68h LRCK/BCK selection of PORT-3 and PORT-4 LBS4[3:0] LBS3[3:0] LBS4[3:0]: LRCK/BCK Selection of PORT-4 (MUX_P4BL) These bits are used for routing LRCK and BCK of PORT-4. Any combination of LRCK1/BCK1 to LRCK6/BCK6 and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-4. Figure 49 shows a detailed diagram of PORT-4. Default value: 0011 0000 Output LRCK1 and BCK1 0001 Output LRCK2 and BCK2 0010 Output LRCK3 and BCK3 0011 Input LRCK4 and BCK4 (default) 0100 Output LRCK5 and BCK5 0101 Output LRCK6 and BCK6 0110 Output LRCK and BCK from DAC12 in master mode 0111 Output LRCK and BCK from DAC34 in master mode 1000 Output LRCK and BCK from ADC12 in master mode 1001 Output LRCK and BCK from ADC34 in master mode Others Reserved Figure 49. Detailed Diagram of PORT-4 78 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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