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PCM5310PAPR bảng dữ liệu(PDF) 54 Page - Texas Instruments |
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PCM5310PAPR bảng dữ liệu(HTML) 54 Page - Texas Instruments |
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54 / 103 page ![]() Register 33 (21h) Register 34 (22h) PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 33 21h System clock output disable RSV RSV SC6D SC5D SC4D SC3D SC2D SC1D SC6D: SCK6 Output Disable SC5D: SCK5 Output Disable SC4D: SCK4 Output Disable SC3D: SCK3 Output Disable SC2D: SCK2 Output Disable SC1D: SCK1 Output Disable These bits are used to disable (low-level output) the clock ports (SCK1, SCK2, SCK3, SCK4, SCK5 and SCK6) in output mode. It is necessary to use these bits with Register 103 (SCS2[2:0], SCS1[2:0]), Register 106 (SCS4[2:0], SCS3[2:0]), and Register 109 (SCS6[2:0], SCS5[2:0]). Each clock port is set to input mode at the default setting. Default value: 1 0 Normal output 1 Disable, low-level output (default) REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 34 22h LRCK and BCK output disable at master mode RSV RSV LB6D LB5D LB4D LB3D LB2D LB1D LB6D: LRCK6 and BCK6 Output Disable LB5D: LRCK5 and BCK5 Output Disable LB4D: LRCK4 and BCK4 Output Disable LB3D: LRCK3 and BCK3 Output Disable LB2D: LRCK2 and BCK2 Output Disable LB1D: LRCK1 and BCK1 Output Disable These bits are used to disable (low-level output) the LRCK/BCK ports (LRCK1/BCK1, LRCK2/BCK2, LRCK3/BCK3, LRCK4/BCK4, LRCK5/BCK5 and LRCK6/BCK6) in output mode. It is necessary to use these bits with Register 101 (LBS2[3:0], LBS1[3:0]), Register 104 (LBS4[3:0], LBS3[3:0]), and Register 107 (LBS6[3:0], LBS5[3:0]). Each LRCK/BCK port is set to input mode at the default setting. Default value: 1 0 Normal output 1 Disable, low-level output (default) 54 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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