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PCM5310PAPR bảng dữ liệu(PDF) 51 Page - Texas Instruments |
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PCM5310PAPR bảng dữ liệu(HTML) 51 Page - Texas Instruments |
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51 / 103 page ![]() Register 28 (1Ch) Register 29 (1Dh) PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 28 1Ch 2.0 Vrms and 2.4 Vrms selection for line output RSV RSV RSV G242 RSV RSV RSV G241 G242: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 2 G241: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 1 The line outputs can drive a 2-VRMS or 2.4-VRMS output with 10 kΩ. The 2.4-VRMS setting is recommend for use when the equipment requires greater than 2-VRMS output. Default value: 0 0 2 VRMS (default) 1 2.4 VRMS REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 29 1Dh Clock halt detection control RSV RSV RSV RSV RSV RSV ACTH CHDE ACTH: Activate Control for Clock Halt Detection CHDE: Enable Clock Halt Detection ACTH is used to control the power up/down for clock halt detection and CHDE is used to enable it. Setting ACTH = CHDE = '1' activates and enables clock halt detection. Clock halt detection can reduce audible noise. The analog outputs are muted when the clock input to DAC12 and DAC34 is suddenly stopped. Default value: 0 ACTH = 0 Deactivate clock halt detection (default) ACTH = 1 Activate clock halt detection CHDE = 0 Clock halt detection disabled (default) CHDE = 1 Clock halt detection enabled Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 51 Product Folder Link(s): PCM5310 |
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