ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

23

DTM <2:0>

Digital Test Control Bits:

The performance of the ML5800 is not specified in these test modes. Although primarily

intended for IC test and debug, they also can help in debugging the radio system. The default (power up) state of these

bits is DTM<2:0> = <0,0,0>. When a non-zero value is written to these fields, the DOUT and PAON pins become a

digital test access port for key digital signals in the transceiver. During normal operation, the DTM field must be set to

zero (see Table 20).

DTM2

DTM1

DTM0

PAON

DOUT

0

0

0

PA Control

Data Out

0

0

1

No Output

AGC Switch State

0

1

0

Prescaler Out Divide 64

PLL Main Divider Output

0

1

1

No Output

PLL Reference Divider Output

1

0

0

PLL 2

PLL 1

1

0

1

No Output

TCAL (Cal. Timer)

1

1

0

3MHz from PLL

LOCKN

1

1

1

No Output

UDLATCH

Table 20: Digital Test Control Bits

TMODE and CFB <6:0>

The TMODE bit disables the automatic filter alignment circuitry, and then the CFB field directly tunes the filter. The CFB

field is a 7 bit binary value that tunes the IF and data filters. The correct value for CFB6 to CFB0 varies depending

upon absolute values of the integrated resistors and capacitors on the chip.

The IF filter center frequency, IF filter

bandwidth, data filter bandwidth and F to V converter center frequency are all tuned together by the CFB field (see

Table 21

).

TMODE

FILTER ALIGNMENT MODE

0

Filters auto aligned during receive slots

1

Filters tuned by CFB<6:0> value

Table 21: TMODE and CFB <6:0> Filter Alignment Test Bits