ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

16

SERIAL BUS CONTROL: EN, DATA, CLK

A 3-wire serial interface is used for programming the ML5800 configuration registers, which control device mode of

operation, pin functions, PLL and reference dividers, internal test modes and filter alignment. Data words are entered

beginning with the MSB. The word is divided into a leading 14-bit data field followed by a 2-bit address field. When the

address field has been decoded the destination register is loaded on the rising edge of EN. Providing less than 16

bits of data will result in unpredictable behavior when EN goes high.

Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift

register by rising edges on the CLK pin. The information is loaded into the addressed latch when EN returns high. This

serial interface bus is an industry standard bus commonly found on PLL devices. It can be efficiently programmed by

either byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal

power when the bus is inactive. See Figure 5 and Table 3.

CLK

Data

EN

t

s

t

h

t

r

t

f

t

ck

t

l

t

se

t

ew

MSB

Figure 5: Serial Bus Timing Diagram

SYMBOL

PARAMETER

MIN

MAX

UNITS

BUS CLOCK (CLK)

Clock input rise time (note 1)

15

ns

Clock input fall time (note 1)

15

ns

Clock period

50

ns

ENABLE (EN)

Minimum pulse width

200

ns

Delay from last clock rising edge to rise of EN

15

ns

Enable set up time to ignore next rising clock

15

ns

BUS DATA (DATA)

Data to clock set up time

15

ns

Data to clock hold time

15

ns

Table 3: Serial Bus Timing Specifications

Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times

can be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and

serial I/O clock rise and fall times are limited to an absolute maximum of 100ns.