ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

18

REGISTER DESCRIPTIONS

A 3-wire serial data input bus sets the ML5800’s transceiver parameters and programs the PLL circuits. Entering 16-bit

words into the ML5800 serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits

are dedicated for data to program the operation and two bits identify the register address. The contents of these

registers cannot be read back.

The three registers are:

Register 0

: PLL Configuration

Register 1

: RF Channel Frequency Configuration

Register 2

: Test Mode Access

Figure 7

shows a register map. Table 4 through Table 21 provide detailed diagrams of the register organization: Table

4

outlines the PLL configuration register (Register 0), Table 17 describes the channel frequency register (Register 1),

and displays the filter tuning and test mode register (Register 2).

Res.

DB13

MSB

B15

DB12

B14

DB11

B13

DB10

B12

DB9

B11

DB8

B10

DB7

B9

DB6

B8

DB5

B7

DB4

B6

DB3

B5

DB2

B4

DB1

B3

DB0

B2

ADR1

B1

ADR0

B0

Res.

V23PLL

NOPD

RCLP

LVLO

TXOL

TXM

TPC

TXCW

LOL

AOUT

RD0

QPP

0

0

N9

DB13

MSB

B15

DB12

B14

DB11

B13

DB10

B12

DB9

B11

DB8

B10

DB7

B9

DB6

B8

DB5

B7

DB4

B6

DB3

B5

DB2

B4

DB1

B3

DB0

B2

ADR1

B1

ADR0

B0

N8

N7

N6

N5

N4

N3

N2

N1

N0

P3

P2

P1

P0

0

1

TMODE

DB13

MSB

B15

DB12

B14

DB11

B13

DB10

B12

DB9

B11

DB8

B10

DB7

B9

DB6

B8

DB5

B7

DB4

B6

DB3

B5

DB2

B4

DB1

B3

DB0

B2

ADR1

B1

ADR0

B0

CFB6

CFB5

CFB4

CFB3

CFB2

CFB1

CFB0

DTM2

DTM1

DTM0

ATM2

ATM1

ATM0

1

0

Register 0: PLL Configuration Register

Register 1: RF Channel Frequency Configuration Register

Register 2: Test Mode Access Register

Data

Data

Data

Address

Address

Address

Figure 7: Configuration Register Map

Power-On State

On power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when VDD ≥

2.0V. The register default values are valid upon power up.

Register Format

The two least significant bits of every register are the address bits ADR <1:0>. Each register is divided into a data field

and address field. The data field is the leading field, while the last two bits clocked into the register are always the

address field. When EN goes high, the address field is decoded and the addressed destination register is loaded. The

last 16 bits clocked into the serial bus are loaded into the register. Clocking in less than 16 bits may result in an

incorrect entry into the register.