ML5800DM datasheet(20/25 Pages) MICRO-LINEAR

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ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

AOUT

Analog Output Mode:

This bit changes the function of the AOUT pin

between an analog data output and transmit power control (see

Table 7

AOUT

AOUT PIN FUNCTION

Transmit Power Control

Data Filter Analog Output

Table 7: AOUT Function Select

LOL

PLL IF Shift:

This bit shifts the PLL by ±1.024MHz in Receive mode

(see Table 8).

LOL

PLL IF SHIFT CONFIGURATION

-1.024MHz LO Shift in Receive

+1.024MHz LO Shift in Receive

Table 8: PLL IF Shift Configuration

TXCW

Transmit Continuous Wave:

This bit produces a continuous wave

(CW) transmitter output for product test when RXON is low (see

Table 9

TXCW

TRANSMIT MODULATION

FSK Modulation

CW – No Modulation

Table 9: Transmit Modulation Mode

TPC

Transmit Power Control:

When the AOUT bit is low, this bit controls

the state of the open-drain output pin. Although this bit can be

changed at any time, the AOUT pin only changes state at the falling

edge of RXON (see Table 10).

TPC

TPC PIN STATE

Pulled to Ground

High Impedance

Table 10: TPC Pin State

TXM

Transmit Mode Bit:

This bit controls the TX RF buffer state timing

mode. It must be reset to 0 for normal operation (see Table 11).

TXM

TXO BUFFER BEHAVIOR

RF Output Always On in TX Mode

RF Output Follows PAON

Table 11: TXM Mode

TXOL

Transmit PLL Mode:

This bit is provided for testing. It disables the

PLL during transmit slots so that the analog modulation path onto the

VCO can be tested without the digital path through the PLL (see

Table 12

TXOL

TRANSMIT PLL MODE

Closed Loop in TX Mode

Open Loop in TX Mode

Table 12: TXOL Operation

LVLO

Low Voltage Lock Out:

The LVLO bit enables a transmit low voltage

lockout latch which shuts off the transmitter by de-asserting the

PAON output. This latch is set if the supply voltage drops below

2.65V and is reset when RXON goes high (see Table 13).

LVLO

PAON BEHAVIOR

PAON Undisturbed

PAON de-asserted when VCCA<2.65V,

Reset by RXON high

Table 13: LVLO Operation

RCLP

RSSI Clip Enable:

The RCLP bit disables the RSSI clipping circuitry.

With RCLP low, the RSSI output voltage is clipped at 1.95V (see

Table 14

RCLP

RSSI BEHAVIOR

RSSI output clipped

RSSI output not clipped

Table 14: RCLP Operation

NODP

PLL Dithering:

This bit removes 2

nd order dither from the fractional-N

PLL when high, reducing the PLL to a 1

st order fractional-N (see

Table 15

NODP

PLL BEHAVIOR

nd order Fractional-N PLL

st order Fractional-N PLL

Table 15: Dithering Operation

V23PLL

Voltage on PLL Regulator:

This bit controls the voltage of the PLL

regulator. It is set to 0 for normal operation. (see Table 17).

V23PLL

REGULATOR BEHAVIOR

PLL Regulator set to 2.7V

PLL Regulator set to 2.3V

Table 16: V23PLL Mode

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