ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

14

CONTROL INTERFACES

There are two sets of control interfaces for the ML5800:

RF Control

:

XCEN, RXON, FREF, RSSI, PAON, AOUT_TPC

Serial Bus Control

:

EN, DATA, CLK

The ML5800 transceiver is used in time division duplex (TDD) mode, where the transceivers at each end of a radio link

alternately transmit and receive. Immediately before data is transmitted or received the ML5800 goes through a ‘self-

calibration’ sequence, where the IF and data filters are frequency aligned while the PLL settles to the carrier frequency.

These calibration cycles are triggered by logic transitions on the control interface. Figure 3 shows the normal operating

cycle for the ML5800.

Tx Data

PAON

RXON

XCEN

t

WAKE

t

RX2TX

DIN

DOUT

TXO

Valid RX Data

t

ED

AOUT_TPC

t

TX2RX

t

MAX

t

MAX

Figure 3: Control Timing for TDD Operation

To implement channel scanning, the ML5800 is kept in RECEIVE mode (XCEN and RXON high) and the PLL is

reprogrammed to select a different RF channel. A filter calibration cycle is initiated by each serial bus write to the

register controlling the PLL modulus, so that filter alignment is updated as the VCO settles to the next programmed

channel frequency. Serial bus writes to other registers do not trigger a calibration cycle. Signal diagram for channel

scanning is shown in Figure 4.

XCEN

DOUT

Valid RX Data

Valid RX Data

EN (Write to PLL

tuning register)

t

WAKE

t

FH

Figure 4: Control Timing when Channel Scanning