7906 datasheet(156/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

8-5

TIMER B

7 to 4

8.2.4 Timer Bi interrupt control register

Figure 8.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer

to “CHAPTER 6. INTERRUPTS.”

8.2 Block description

Fig. 8.2.4 Structure of timer Bi interrupt control register

(1)

Interrupt priority level select bits (bits 2 to 0)

These bits are used to select a timer Bi interrupt’s priority level. When using timer Bi interrupts,

select the priority level from levels 1 through 7. When a timer Bi interrupt request occurs, its priority

level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is

enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt

disable bit (I) = “0.”) To disable timer Bi interrupts, set these bits to “0002” (level 0).

(2)

Interrupt request bit (bit 3)

This bit is set to “1” when a timer Bi interrupt request occurs. This bit is automatically cleared to “0”

when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by

software.

Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16)

Interrupt priority level select bits

Interrupt request bit

Nothing is assigned.

b7 b6 b5 b4 b3 b2 b1 b0

Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

0 : No interrupt requested

1 : Interrupt requested

Undefined

(Note)

—

Bit name

Bit

Function

At reset

R/W

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