7906 datasheet(84/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

6-5

INTERRUPTS

6.3 Interrupt control

The maskable interrupts are controlled by the following :

•Interrupt request bit

•Interrupt priority level select bits

•Processor interrupt priority level (IPL)

•Interrupt disable flag (I)

Figure 6.3.1 shows the memory assignment of the interrupt control registers, and Figures 6.3.2 shows their

structures.

}

Assigned to an interrupt control register of each interrupt.

Assigned to the processor status register (PS).

6.3 Interrupt control

Fig. 6.3.1 Memory assignment of interrupt control registers

7016

7116

7216

7416

7516

7616

7716

7816

7916

7A16

7B16

7C16

7316

Address

6F16

6E16

A-D conversion interrupt control register

UART0 transmit interrupt control register

UART1 transmit interrupt control register

UART0 receive interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

INT4 interrupt control register

INT3 interrupt control register

F616

F716

F816

FD16

FE16

FF16

F916

F516

Timer A5 interrupt control register

Timer A6 interrupt control register

Timer A7 interrupt control register

Timer A8 interrupt control register

Timer A9 interrupt control register

INT7 interrupt control register

INT6 interrupt control register

INT5 interrupt control register

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