7906 datasheet(34/531 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7906 Group User’s Manual Rev.2.0

2-13

2.2 Bus interface unit (BIU)

Internal address bus

φBIU

Internal data bus

RD: Data to be read, WD: Data to be written

Note 2: The above waveforms apply when bus cycle = 2

φ.

For the bus cycles at access to the internal area, see Table 2.2.4.

Internal address bus

(AD0

–AD23)

φBIU

Internal data bus

(DB0

–DB7)

(even)

(a) When accessing 8-bit data (Note 1) or accessing 16-bit data starting from an even-numbered address

Internal data bus

(DB8

–DB15)

(odd)

WD (even)

WD (odd)

Address

WD (odd)

Internal address bus

φBIU

Internal data bus

(odd)

Address

Address + 1

(even)

WD (even)

(odd)

(even)

WD (even)

(even)

WD (even)

WD(odd)

(odd)

WD (odd)

(odd)

Address

Address + 1

(even)

WD (even)

Address + 3

WD (odd)

(odd)

WD (even)

WD (odd)

Note 1: When reading 8-bit data at an even-numbered address, only RD (even)

will be taken into a data buffer.

When reading 8-bit data at an odd-numbered address, only RD (odd)

will be taken into a data buffer.

When writing 8-bit data to an even-numbered address, only WD (even)

will be written to the address.

When writing 8-bit data to an odd-numbered address, only WD (odd)

will be written to the address.

Internal address bus

φBIU

Internal data bus

Address

Address + 2

(b) When accessing 16-bit data starting from an odd-numbered address

(d) When accessing 32-bit data starting from an odd-numbered address

(even)

(AD0

–AD23)

(DB0

–DB7)

(DB8

–DB15)

(AD0

–AD23)

(DB0

–DB7)

(DB8

–DB15)

(AD0

–AD23)

(DB0

–DB7)

(DB8

–DB15)

Fig. 2.2.4 Operation waveform examples at reading from or writing to internal area

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