7906 datasheet(85/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-6

Fig. 6.3.2 Structure of interrupt control register

6.3 Interrupt control

7 to 4

A-D conversion, UART0 and 1 transmit, UART0 and 1 receive,

timers A0 to A4, timers B0 to B2 interrupt control registers

(Addresses 7016 to 7C16)

Timers A5 to A9 interrupt control registers (Addresses F516 to F916)

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt priority level select bits

Interrupt request bit

Nothing is assigned.

Notes 1: The A-D conversion interrupt request bit is undefined after reset.

2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

0 : No interrupt requested

1 : Interrupt requested

(Note 1)

Undefined

(Note 2)

—

Bit name

Bit

Function

At reset

R/W

7, 6

INT3 to INT7 interrupt control registers (Addresses 6E16, 6F16, FD16, FE16, FF16)

Interrupt priority level select bits

Interrupt request bit (Note 1)

Polarity select bit

Level sense/Edge sense select

bit

Nothing is assigned.

b7 b6 b5 b4 b3 b2 b1 b0

Notes 1: The interrupt request bits of INT3 to INT7 interrupts are invalid when the level sense is selected.

2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

0 : No interrupt requested

1 : Interrupt requested

0 : The interrupt request bit is set to “1” at “H” level

when level sense is selected; this bit is set to “1”

at falling edge when edge sense is selected.

1 : The interrupt request bit is set to “1” at “L” level

when level sense is selected; this bit is set to “1”

at rising edge when edge sense is selected.

0 : Edge sense

1 : Level sense

Undefined

(Note 2)

—

Bit name

Bit

Function

At reset

R/W

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