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7906 bảng dữ liệu(PDF) 141 Page - Renesas Technology Corp

tên linh kiện 7906
Giải thích chi tiết về linh kiện  16-BIT SINGLE-CHIP MICROCOMPUTER
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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TIMER A
7906 Group User’s Manual Rev.2.0
7-38
7.6 Pulse width modulation (PWM) mode
7.6 Pulse width modulation (PWM) mode
Timer Aj (j = 0 to 2, 4, 9) is equipped with the pulse width modulation (PWM) mode.
In this mode, the timer continuously outputs pulses which have an arbitrary width. Table 7.6.1 lists the
specifications of the PWM mode. Figure 7.6.1 shows the structures of the timer Aj register and timer Aj
mode register in the PWM mode.
Each of timers A3, A5 to A8 is not equipped with this mode.
Table 7.6.1 Specifications of PWM mode
Item
Count source fi
Count operation
PWM period/“H” level width
Count start condition
Count stop condition
Interrupt request occurrence timing
TAjIN pin’s function
TAjOUT pin’s function
Read from timer Aj register
Write to timer Aj register
Specifications
f1, f2, f16, f64, f512, or f4096
q Countdown (operating as an 8-bit or 16-bit pulse width modulator)
q Reload register’s contents are reloaded at rising edge of PWM pulse,
and counting continues.
q A trigger generated during counting does not affect the counting.
<16-bit pulse width modulator>
<8-bit pulse width modulator>
q When a trigger is generated. (Note)
q Internal or external trigger can be selected by software.
When the count start bit is cleared to “0.”
At falling edge of PWM pulse
Programmable I/O port pin or trigger input pin
PWM pulse output
An undefined value is read out.
q While counting is stopped
When a value is written to the timer Aj register, it is written to both
of the reload register and counter.
q While counting is in progress
When a value is written to the timer Aj register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
Period =
(216–1)
fi
[s]
“H” level width =
[s]
Period =
(m + 1)(28–1)
fi
“H” level width =
[s]
n(m + 1)
fi
n : Timer Aj register’s set value
[s]
m : Timer Aj register’s low-order 8
bits’ set value
n : Timer Aj register’s high-order
8 bits’ set value
Note: The trigger is generated with the count start bit = “1.”
n
fi



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