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7733 bảng dữ liệu(PDF) 241 Page - Renesas Technology Corp

tên linh kiện 7733
Giải thích chi tiết về linh kiện  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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SERIAL I/O
7733 Group User’s Manual
8–38
8.3 Clock synchronous serial I/O mode
[When not using interrupts]
[When using interrupts]
A UARTi receive interrupt request occurs
when reception is completed.
UARTi receive interrupt
This diagram indicates bits and registers
required for processing.
Refer to Figure 8.3.15 for details about the
change of flag status and the occurrence timing
of an interrupt request.
Processing after reading out receive data
UART0 receive buffer register (address 36 16)
UART1 receive buffer register (address 3E 16)
UART2 receive buffer register (address 6A 16)
b7
b0
Reading of the receive data
Receive data is read out.
UART0 transmit/receive control register 1 (address 35 16)
UART1 transmit/receive control register 1 (address 3D 16)
UART2 transmit/receive control register 1 (address 69 16)
b7
b0
Receive completion flag
0: Reception is not completed.
1: Reception is completed.
Checking the completion of reception
1
1
UART0 transmit/receive control register 1 (address 35 16)
UART1 transmit/receive control register 1 (address 3D 16)
UART2 transmit/receive control register 1 (address 69 16)
b7
b0
Checking the error
Overrun error flag
0: No overrun error is detected.
1: Error is detected.
1
1
g
Fig. 8.3.12 Processing after reception is completed



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