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7733 Group User's Manual

INTERRUPTS

4–8

4.3.1 Interrupt disable flag (I)

This flag can disable all maskable interrupts. When this flag is set to “1,” all maskable interrupts are

disabled; when this flag is cleared to “0,” all maskable interrupts are enabled. Because this flag is set to

“1” at reset, clear this flag to “0” when enabling interrupts.

This flag is allocated to the processor status register (PS).

4.3.2 Interrupt request bit

When an interrupt request occurs, this bit is set to “1.” And then, this bit remains set to “1” until the interrupt

request is accepted; this bit is cleared to “0” when the interrupt request is accepted.

This bit can be set to “1” or cleared to “0” by software, also.

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Note that when an INTi interrupt is used with the level sense selected, the INTi interrupt request bit (i = 0

to 2) is ignored.

4.3.3 Interrupt priority level selection bits and Processor interrupt priority level (IPL)

The interrupt priority level selection bits are used to set the priority level of an interrupt.

When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority

level (IPL). Only when the comparison result satisfies the following relationship, the interrupt request is

enabled. Therefore, by setting the interrupt priority level to 0, the interrupt can be disabled.

The processor interrupt priority level (IPL) is allocated to the processor status register (PS).

Interrupt priority level > Processor interrupt priority level (IPL)

Table 4.3.1 lists the settings of interrupt priority levels. Table 4.3.2 lists the relationship between the IPL’s

contents and enabled interrupt priority levels.

The interrupt disable flag (I), interrupt request bit, interrupt priority level selection bits, and processor

interrupt priority level (IPL) are independent of each other; they do not affect each other. Interrupt requests

are accepted only when the following conditions are satisfied.

q Interrupt disable flag (I) = “0”

q Interrupt request bit = “1”

q Interrupt priority level > Processor interrupt priority level (IPL)

4.3 Interrupt control

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