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7733 bảng dữ liệu(PDF) 51 Page - Renesas Technology Corp |
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7733 bảng dữ liệu(HTML) 51 Page - Renesas Technology Corp |
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51 / 940 page  CENTRAL PROCESSING UNIT (CPU) 7733 Group User’s Manual 2–12 2.2.2 Functions of bus interface unit (BIU) The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists each register’s function. 2.2 Bus interface unit Table 2.2.1 Each register’s function Fig. 2.2.2 Registers’ structure of which bus interface unit (BIU) consists Name Program address register Instruction queue buffer Data address register Data buffer Functions Indicates a store address for an instruction which is next fetched into an instruction queue buffer. Temporarily stores an instruction which was fetched. Indicates an address for data which is next read or written. Temporarily stores data which was read from the memory • I/O unit by the BIU or which is to be written to the memory • I/O unit by the CPU. PA b23 b0 Q0 b7 b0 Q1 Q2 DA b23 b0 DBL b0 DBH b15 Program address register Instruction queue buffer Data address register Data buffer |
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