7733 datasheet(85/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–6

A-D

/UART2 trans./rece. interrupt control register

UART0 transmission interrupt control register

UART0 receive interrupt control register

UART1 transmission interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

INT0

interrupt control register

INT1

interrupt control register

INT2

/Key input interrupt control register

Address

7016

7116

7216

7316

7416

7516

7616

7716

7816

7916

7A16

7B16

7C16

7D16

7E16

7F16

4.3 Interrupt control

Maskable interrupts are enabled or disabled by setting the following:

qInterrupt request bit

qInterrupt priority level selection bits

qProcessor interrupt priority level (IPL)

qInterrupt disable flag (I)

The interrupt disable flag (I) and processor interrupt priority level (IPL) are allocated to the processor status

interrupt control register for the corresponding interrupt.

Figure 4.3.1 shows the memory map of interrupt control registers and Figure 4.3.2 shows their structures.

qMaskable interrupts

: By software, acceptance of these interrupts’ requests can be disabled.

qNon-maskable interrupts (Zero division, BRK instruction, and watchdog timer interrupts)

: When an interrupt request occurs, it is certain to be accepted. They do not

have interrupt control registers and are not affected by the interrupt disable

flag (I).

4.3 Interrupt control

Fig. 4.3.1 Interrupt control registers’ memory map

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