7733 datasheet(207/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–4

Note: The bit converter, the polarity reversing circuit and RTSi output function are not assigned

for UART2.

n: Value set to the UARTi baud rate register

Divider [1/(n+1)]

UART2 (Address 6516)

Divider(1/16 )

CLKi

CTSi / RTSi

000 000 0 D8 D7 D6 D5 D4 D3 D2 D1 D0

Data bus (odd)

Transfer clock

Receive control

circuit

Transmission

control circuit

Transmission register

D8 D7 D6 D5 D4 D3 D2 D1 D0

UART0 (Addresses 3716, 3616)

Receive buffer register

UART1 (Addresses 3F16, 3E16)

Transmission buffer register

Divider(1/16 )

UART transmission

Divider (1/2 )

f16

f64

f512

Clock synchronous (When internal clock is selected)

UART receive

Clock synchronous

(Internal clock)

Clock synchronous

(External clock)

Internal

External

Baud rate register

UART0 (Address 3116)

Clock source selection

RxDi

TxDi

Bit converter

Receive register

Data bus (odd)

Bit converter

Polarity reversing circuit

Data bus (even)

UART2 (Addresses 6B16, 6A16)

(Note)

Data bus (even)

Transfer clock

UART0 (Addresses 3316, 3216)

UART1 (Addresses 3B16, 3A16)

UART2 (Addresses 6716, 6616)

UART1 (Address 3916)

8.2 Block description

Figure 8.2.1 shows the block diagram for serial I/O. Registers related to serial I/O are described below.

8.2 Block description

Fig. 8.2.1 Block diagram for serial I/O

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