7733 datasheet(697/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–21

: Ready state

: Software wait

• One of signals RDE, WEL, and WEH

• Signals WEL and WEH

g One of the following is applied.:

<<No wait>>

Sampling timing

Clock

CPU

RDY

ALE

Bus is not in use.

Bus is in use.

Ready state is terminated.

“L” level which is input to pin RDY is

accepted, so that signal g is stopped

at “H” level for 1cycle of clock

(area

), and

CPU

is stopped

at “L” level.

“L” level which is input to pin RDY

is not accepted, but

CPU

is stopped at

“L” level.

“L” level which is input to pin RDY

is accepted, so that signal g is stopped

at “L” level for 1cycle of clock

(area

), and

CPU

is stopped at

“L” level.

“L” level which is input to pin RDY is not

accepted because it is sampled

immediately before a wait generated by

software wait (area

), but

CPU

stopped at “L” level.

Sampling timing

Clock

CPU

RDY

ALE

<<Wait 0>>

Bus is in use.

Sampling timing

Clock

CPU

RDY

ALE

<<Wait 1>>

Bus is in use.

_____

Fig. 12.3.2 Timings when ready state is accepted and terminated (when not using signal RSMP)

12.3 Ready function

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