7733 datasheet(628/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-80

Appendix 9. Q & A

Use the STA and LDM instructions for setting the registers or the bits listed below.

Do not use read-modify-write instructions (for example, CLB, SEB, INC, DEC, ASL, LSR, ROL,

and ROR).

UART0 baud rate register (address 3116)

UART1 baud rate register (address 3916)

UART2 baud rate register (address 6516)

UART0 transmission buffer register (addresses 3316, 3216)

UART1 transmission buffer register (addresses 3B16, 3A16)

UART2 transmission buffer register (addresses 6716, 6616)

Timer A4 two-phase pulse signal processing selection bit (bit 7 at address 4416)

Timer A3 two-phase pulse signal processing selection bit (bit 6 at address 4416)

Timer A2 two-phase pulse signal processing selection bit (bit 5 at address 4416)

When writing data to the oscillation circuit control register 1 (address 6F16), be sure to follow the

procedure shown below.

• When initializing the clock prescaler

Write data “8016.” (LDM instruction)

↓

Clock prescaler is reset.

• When writing to bits 0 to 2

Write data “010101012.” (LDM instruction)

↓

Write data “00001!!!2.” (LDM instruction) (Note)

↓

Bits 0 to 2 are set.

Note: In the case of the 7735 Group, write data “00000!!!2.”

When writing data to the memory allocation control register (address 6316), be sure to follow the

procedure shown below.

Write data “010101012.” (LDM instruction)

↓

Write data “00000!!!2.” (LDM instruction)

↓

Bits 0 to 2 are set.

SFR

Is there any SFR where a certain write instruction can not be used?

Next instruction

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