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7733 Group User’s Manual

21-79

APPENDIX

Processor mode

Although when the processor mode bits are set in order to switch the processor mode, as described

above, the mode is not switched until the write cycle for the processor mode bits is completed. (The

processor mode is actually switched simultaneously with the write cycle’s completion.)

At this time, the program counter indicates the address which is next to the address (address XXXX16)

where the write instruction for the processor mode bits is stored. Also, access to the internal ROM

area is disabled. Note that there is a possibility that less than four bytes of instructions are prefetched

into instruction queue buffers. Therefore, the address which resides in the external ROM area and is

accessed first after the mode is switched is one of addresses “XXXX16 + 1” to “XXXX16

4.” Note

also that instructions at addresses “XXXX16

1” to “XXXX16

3” in the internal ROM area may be

executed. To solve this problem, do the following processes by software.

[Process ]

Program a write instruction for the processor mode bits and the following instructions (at least three

bytes) to the same addresses of the internal ROM and external ROM areas. (See below.)

[Process ]

Transfer a write instruction for the processor mode bits to an internal RAM area and make the program

branch to the address in order to execute the write instruction. And then, make the program branch to

the program address in the external ROM area. (Contents of instruction queue buffers are initialized by

a branch instruction.)

LD M ,B #00000010B, PM R

NO P

LD M ,B #00000010B, PM R

NO P

XXXX16

External ROMarea

Internal

ROM area

XXXX16

At least

three

When the processor mode is switched, as described below, by setting the processor mode bits (bits

1 and 0 at address 5E16) while a program is executed, is there any precaution on software?

Single-chip mode

Microprocessor mode

Memory expansion mode

Microprocessor mode

Appendix 9. Q & A

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