7733 datasheet(536/940 Pages) RENESAS

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EXTERNAL ROM VERSION

7733 Group User’s Manual

20–20

20.7 Timer A

(3) Initial setting example for registers related to pulse output port mode

Figures 20.7.7 to 20.7.9 show an initial setting example for registers related to the pulse output port

mode.

Fig. 20.7.7 Initial setting example for registers related to pulse output port mode (1)

Setting of the pulse output data register 0 and pulse output data register 1

Pulse output data register 0 (address 1D 16)

Continued to

“Initial setting example for registers related to pulse output port mode (2)”

on the next page

RTP00

RTP01

RTP02

RTP03

Setting of the division ratio for timer A0 or timer A2

Values 000016 to FFFF16 (n) can be set.

(b15)

(b8)

Timer A0 register (addresses 47 16, 4616)

Timer A2 register (addresses 4B 16, 4A16)

g Counter divides the count source by (n + 1).

Count source selection bits

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

Setting of the timer A0 mode register or timer A2 mode register

Timer A0 mode register (address 56 16)

Timer A2 mode register (address 5A 16)

b7 b6

X: It may be “0” or “1.”

Output data is set to the corresponding bit.

Pulse output data register 1 (address 1C 16)

RTP10

RTP11

RTP12

RTP13

Output data is set to the corresponding bit.

0 !

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