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SH7721 bảng dữ liệu(PDF) 195 Page - Renesas Technology Corp

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Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 133 of 1458
REJ09B0033-0300
3.5.6
ALU Logical Operations
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point operations as shown in table 3.21.
As shown in figure 3.15, this type of operation uses only the upper word of each operand. The
lower word and guard-bit parts are ignored for the source operand and those of the destination
operand are automatically cleared. These operations are also executed in the DSP stage, as shown
in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
31
31
31
39
39
39
Ignored
Cleared to 0
0
Source 1
0
Destination
ALU
DSR
0
Source 2
GT
Z
N
V DC
Figure 3.15 ALU Logical Operation Flow
Table 3.24
Variation of ALU Logical Operations
Mnemonic
Function
Source 1
Source 2
Destination
PAND
Logical AND
Sx
Sy
Dz
POR
Logical OR
Sx
Sy
Dz
PXOR
Logical exclusive OR
Sx
Sy
Dz



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