SH7721 datasheet(192/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 130 of 1458

REJ09B0033-0300

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Signed Greater Than Mode: CS[2:0] = B'100

The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data

(signed) as the result of compare operation PCMP. The PCMP operation should be executed

before executing the conditional operation under this condition mode. This mode is similar to the

Negative Value Mode described before, because the result of a compare operation is a positive

value if the source 1 data is greater than the source 2 data. However, the signed bit of the result

shows a negative value if the compare operation yields a result beyond the range of the destination

operand, including the guard-bit parts (called “Over-range”), even though the source 1 data is

greater than the source 2 data. The DC bit is updated concerning this type of special case in this

condition mode. The equation below shows the definition of getting this condition:

DC = ~ {(Negative ^ Over-range) | Zero}

When the PCMP operation is executed under this condition mode, the result of the DC bit is the

same as the T bit’s result of the CMP/GT operation of the CPU instruction.

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Signed Greater Than or Equal Mode: CS[2:0] = B'101

The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2

data (signed) as the result of compare operation PCMP. This mode is similar to the Signed Greater

Than Mode described before but the equal case is also included in this mode. The equation below

shows the definition of getting this condition:

DC = ~ (Negative ^ Over-range)

When the PCMP operation is executed under this condition mode, the result of the DC bit is the

same as the T bit’s result of a CMP/GE operation of the CPU instruction.

The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]

bits. See the negative value mode part above. The Z bit always indicates the same state as the DC

bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit

always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the

overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed

greater than mode by the CS[2:0] bits. See the signed greater than mode part above.

Note:

The DC bit is always updated as the carry flag for ‘PADDC’ and is always updated as the

carry/borrow flag for ‘PSUBC’ regardless of the CS[2:0] state.

• Overflow Protection

The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See

section 3.5.11, Overflow Protection, for details.

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