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SH7721 bảng dữ liệu(PDF) 188 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 126 of 1458
REJ09B0033-0300
Table 3.21
Variation of ALU Fixed-Point Operations
Mnemonic
Function
Source 1
Source 2
Destination
PADD
Addition
Sx
Sy
Dz (Du)
PSUB
Subtraction
Sx
Sy
Dz (Du)
PADDC
Addition with carry
Sx
Sy
Dz
PSUBC
Subtraction with borrow
Sx
Sy
Dz
PCMP
Comparison
Sx
Sy
Sx
All 0
Dz
PCOPY
Data copy
All 0
Sy
Dz
Sx
All 0
Dz
PABS
Absolute
All 0
Sy
Dz
Sx
All 0
Dz
PNEG
Negation
All 0
Sy
Dz
PCLR
Clear
All 0
All 0
Dz
Table 3.22
Correspondence between Operands and Registers
Register
Sx
Sy
Dz
Du
A0
Yes
Yes
Yes
A1
Yes
Yes
Yes
M0
Yes
Yes
M1
Yes
Yes
X0
Yes
Yes
Yes
X1
Yes
Yes
Y0
Yes
Yes
Yes
Y1
Yes
Yes
As shown in figure 3.10, data loaded from the memory at the MA stage, which is programmed at
the same line as the ALU operation, is not used as a source operand for this operation, even
though the destination operand of the data load operation is identical to the source operand of the
ALU operation. In this case, previous operation results are used as the source operands for the
ALU operation, and then updated as the destination operand of the data load operation.



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