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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SH7721 bảng dữ liệu(PDF) 35 Page - Renesas Technology Corp |
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SH7721 bảng dữ liệu(HTML) 35 Page - Renesas Technology Corp |
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35 / 1524 page  Rev. 3.00 Jan. 18, 2008 Page xxxv of lxii Figures Section 1 Overview Figure 1.1 Block Diagram ............................................................................................................ 10 Figure 1.2 Pin Assignments (PLBG0256GA-A (BP-256H/HV))................................................. 11 Figure 1.3 Pin Assignments (PLBG0256KA-A (BP-256C/CV)) ................................................. 12 Section 2 CPU Figure 2.1 Processing State Transitions........................................................................................ 38 Figure 2.2 Virtual Address to External Memory Space Mapping................................................. 41 Figure 2.3 Register Configuration in Each Processing Mode....................................................... 44 Figure 2.4 General Registers ........................................................................................................ 46 Figure 2.5 System Registers and Program Counter ...................................................................... 47 Figure 2.6 Control Register Configuration ................................................................................... 51 Figure 2.7 Data Format on Memory (Big Endian Mode) ............................................................. 52 Figure 2.8 Data Format on Memory (Little Endian Mode) .......................................................... 53 Section 3 DSP Operating Unit Figure 3.1 DSP Instruction Format............................................................................................... 82 Figure 3.2 CPU Registers in DSP Mode....................................................................................... 84 Figure 3.3 DSP Register Configuration ........................................................................................ 88 Figure 3.4 DSP Registers and Bus Connections......................................................................... 101 Figure 3.5 General Registers (DSP Mode) ................................................................................. 104 Figure 3.6 Sample Parallel Instruction Program......................................................................... 119 Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 121 Figure 3.8 Data Formats ............................................................................................................. 124 Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 125 Figure 3.10 Operation Sequence Example.................................................................................. 127 Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 128 Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 129 Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 129 Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 131 Figure 3.15 ALU Logical Operation Flow ................................................................................. 133 Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 135 Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 137 Figure 3.18 Logical Shift Operation Flow.................................................................................. 139 Figure 3.19 PDMSB Operation Flow ......................................................................................... 141 Figure 3.20 Rounding Operation Flow ....................................................................................... 145 Figure 3.21 Definition of Rounding Operation........................................................................... 145 |
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