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SH7708 bảng dữ liệu(PDF) 212 Page - Renesas Technology Corp |
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SH7708 bảng dữ liệu(HTML) 212 Page - Renesas Technology Corp |
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212 / 633 page ![]() 194 Table 10.3 Physical Address Space Map Area Physical Address Connectable Memory Capacity Access Size 0 H'00000000 to H'03FFFFFF Normal memory*1, burst 64 Mbytes 8, 16, 32*2 H'00000000 + H'20000000 × n to H'03FFFFFF + H'20000000 × n ROM Shadow n: 1–6 1 H'04000000 to H'07FFFFFF Normal memory 64 Mbytes 8, 16, 32*3 H'04000000 + H'20000000 × n to H'07FFFFFF + H'20000000 × n Shadow n: 1–6 2 H'08000000 to H'0BFFFFFF Normal memory, 64 Mbytes 8, 16, 32*3, *4 H'08000000 + H'20000000 × n to H'0BFFFFFF + H'20000000 × n synchronous DRAM, DRAM Shadow n: 1–6 3 H'0C000000 to H'0FFFFFFF Normal memory, 64 Mbytes 8, 16, 32*3, *5 H'0C000000 + H'20000000 × n to H'0FFFFFFF + H'20000000 × n synchronous DRAM, DRAM, pseudo-SRAM Shadow n: 1–6 4 H'10000000 to H'13FFFFFF Normal memory 64 Mbytes 8, 16, 32*3 H'10000000 + H'20000000 × n to H'13FFFFFF + H'20000000 × n Shadow n: 1–6 5*5 H'14000000 to H'15FFFFFF Normal memory, PCMCIA, 32 Mbytes 8, 16, 32 *3, *6 H'16000000 to H'17FFFFFF burst ROM 32 Mbytes H'14000000 + H'20000000 × n to H'17FFFFFF + H'20000000 × n Shadow n: 1–6 6 H'18000000 to H'19FFFFFF Normal memory, PCMCIA, 32 Mbytes 8, 16, 32 *3, *6 H'1A000000 to H'1BFFFFFF burst ROM H'18000000 + H'20000000 × n to H'1BFFFFFF + H'20000000 × n Shadow n: 1–6 7*7 H'1C000000 + H'20000000 × n to H'1FFFFFFF + H'20000000 × n Reserved area n: 0–7 Notes: 1. Memory with an SRAM, ROM, or similar interface 2. Memory bus width specified by external pin 3. Memory bus width specified by register 4. With synchronous DRAM interface, bus width is 32 bits only. With DRAM interface, bus width is 16 bits only. 5. With synchronous DRAM interface, bus width is 32 bits only. With DRAM and pseudo-SRAM interface, bus width is either 16 or 32 bits only. When areas 2 and 3 are both DRAM interface areas, bus width is 16 bits only. 6. With PCMCIA interface, bus width is either 8 or 16 bits only. 7. Do not access a reserved area, as operation cannot be guaranteed in this case. |
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