SH7708 datasheet(50/633 Pages) RENESAS

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Table 2.5

Instruction Code Format

Item

Format

Explanation

Instruction

mnemonic

OP.Sz SRC,DEST

OP: Operation code

Sz: Size

SRC: Source

DEST: Destination

Rm: Source register

Rn: Destination register

imm: Immediate data

disp: Displacement

Instruction

code

MSB

↔ LSB

mmmm: Source register

nnnn: Destination register

0000: R0

0001: R1

...........

1111: R15

iiii: Immediate data

dddd: Displacement

Operation

→, ←

(xx)

M/Q/T

∧

<<n, >>n

Direction of transfer

Memory operand

Flag bits in SR

Logical AND of each bit

Logical OR of each bit

Exclusive OR of each bit

Logical NOT of each bit

n-bit shift

Privileged

mode

Indicates whether privileged mode applies

Execution

cycles

Value when no wait states are inserted

The execution cycles listed in the table are minimums. The

actual number of cycles may be increased in cases such

as the following:

1. When contention occurs between instruction fetches

and data access

2. When the destination register of the load instruction

(memory

→ register) and the register used by the next

instruction are the same

T bit

Value of T bit after instruction is executed

—: No change

Note:

Scaling (

×1, ×2, ×4) is performed according to the instruction operand size.

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