SH7708 datasheet(209/633 Pages) RENESAS

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191

Table 10.1

Pin Configuration (Preliminary) (cont)

Pin Name

Signal

I/O

Description

Data enable 0

DQMLL/

WE0

When synchronous DRAM is used, selects D7–D0.

For other memory, D7–D0 write strobe signal.

Data enable 1

DQMLU/

WE1

When synchronous DRAM is used, selects D15–D8.

When PCMCIA is used, strobe signal that indicates

the write cycle. For other memory, D15–D8 write

strobe signal.

Data enable 2

DQMUL/

WE2/

ICIORD

When synchronous DRAM is used, selects D23–

D16. For other memory, D23–D16 write strobe

signal. For PCMCIA, strobe signal indicating I/O

read.

Data enable 3

DQMUU/

WE3/

ICIOWR

When synchronous DRAM is used, selects D31–

D24. For other memory, D31–D24 write strobe

signal. For PCMCIA, strobe signal indicating I/O

write.

Read

Strobe signal indicating read cycle

Wait

WAIT

Wait state request signal (synchronous signal)

16-bit I/O

IOIS16

Signal indicating PCMCIA 16-bit I/O. Valid only in

little-endian mode. (Fix low in big-endian mode.)

Clock enable

CKE

Connected to clock enable control signal of

synchronous DRAM

Bus release

request

BREQ

Bus release request signal

Bus release

acknowledgment

BACK

Bus release acknowledge signal

Area 0 bus width,

PCMCIA card

select

MD3/

CE2A*

MD4/

CE2B*

I/O

Signal controlling bus width of physical space area

0. When PCMCIA is used,

CE2A and CE2B.

Endian switching/

low address strobe

MD5/

RAS2*

I/O

Signal setting endian for all spaces on reset. When

area 2 DRAM is connected, area 2 DRAM

RAS

signal

Notes: 1. MD3/

CE2A input/output switching is performed by BCR1.A5PCM. Output is selected

when BCR1.A5PCM = 1.

2. MD4/

CE2B input/output switching is performed by BCR1.A6PCM. Output is selected

when BCR1.A6PCM = 1.

3. MD5/

RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected

when BCR1.DRAMTP (2–0) = 101.

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