SH7708 datasheet(214/633 Pages) RENESAS

214 / 633 page

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Shadow Space: Areas 0–6 are decoded by physical address bits A28–A26, which correspond to

areas 000 to 110. Address bits 31–29 are ignored. This means that the range of area 0 addresses,

for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address

space obtained by adding to it H'20000000

× n (n = 1–6). The address range for area 7, which is

on-chip I/O space, is H'FC000000 to H'FFFFFFF. The address space H'1C000000 + H'20000000

n–H'1FFFFFFF + H'20000000

× n (n = 0–6) corresponding to the area 7 shadow space is reserved,

so should not be used.

10.1.6

PCMCIA Support

The SH7708 Series supports PCMCIA standard interface specifications in physical space areas 5

and 6.

The interface supported is basically the IC memory card interface and I/O card interface defined

by PCMCIA Specifications Version 4.2. In addition, burst access is supported to enable high-

speed access.

Physical space area 5 supports the IC memory card interface only; area 6 supports both the IC

memory card interface and the I/O card interface.

Table 10.4

PCMCIA Interface Characteristics

Item

Characteristics

Access

Random access + burst access (ROM page mode correspondence added)

Data bus

8/16 bits

Memory type

Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM

Memory capacity

Maximum 32 Mbytes

I/O section capacity

Maximum 32 Mbytes

Other

Supports dynamic I/O bus sizing* and access to PCMCIA interface from

both the address translation area and non-address translation area

Note: * Dynamic I/O bus sizing is supported only in little-endian mode.

Common memory/Attribute memory

Area 5: H'14000000

Area 5: H'16000000

Common memory/Attribute memory

Area 6: H'18000000

I/O space

Area 6: H'1A000000

Figure 10.4 PCMCIA Space Allocation

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