SH7052 datasheet(625/919 Pages) RENESAS

625 / 919 page

599

AUDCK

Not ready

Ready

DIR

Ready Ready

0000

1110

0001

A31–A28

D3–D0

D31–D28

A3–A0

AUDSYNC

AUDATAn

Input/output switchover

Input

Output

Figure 17.6 Example of Write Operation (Longword Read)

AUDCK

Not ready

DIR

Ready

(Bus error)

Ready

(Bus error)

Ready

(Bus error)

0101

0000

1010

0101

A31–A28

A3–A0

AUDSYNC

AUDATAn

Input/output switchover

Input

Output

Figure 17.7 Example of Error Occurrence (Longword Read)

17.5

Usage Notes

17.5.1

Initialization

The debugger’s internal buffers and processing states are initialized in the following cases:

1. In a power-on reset

2. In hardware standby mode

3. When

AUDRST is driven low

4. When the

AUDSRST bit is set to 1 in the SYSCR register (see section 23.2.2)

5. When the MSTOP3 bit is set to 1 in the MSTCR register (see section 23.2.3)

17.5.2

Operation in Software Standby Mode

The debugger is not initialized in software standby mode. However, since the

SH7052F/SH7053F/SH7054F’s internal operation halts in software standby mode:

1. When AUDMD is high (RAM monitor mode): Ready is not returned (Not Ready continues to

be returned)

However, when operating on an external clock, the protocol continues.

2. When AUDMD is low (PC trace): Operation stops. However, operation continues when STBY

is released.

SH7052 bảng dữ liệu(PDF) 625 Page - Renesas Technology Corp

SH7052 bảng dữ liệu(HTML) 625 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL