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SH7052 bảng dữ liệu(PDF) 622 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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If another branch occurs during branch destination address output, the later branch has priority for
output. In this case,
AUDSYNC is negated and the AUDATA pins output the address after
outputting 10xx again (figure 17.3 shows an example of the output when consecutive branches
occur). Note that the compared address is the previous fully output address, and not an interrupted
address (since the upper address of an interrupted address will be unknown).
The interval from the start of execution at the branch destination address in the PC until the
AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles.
AUDCK
0011
0011
1011
A3–A0
A7–A4
A11–A8 A15–A12 A19–A16 A23–A20 A27–A24 A31–A28
0011
AUDSYNC
AUDATA [3:0]
Start of execution at branch destination address in PC
Figure 17.2 Example of Data Output (32-Bit Output)
AUDCK
0011
0011
1011
A3–A0
0011
0011
A3–A0
A7–A4
1010
A7–A4
A11–A8 A15–A12
AUDSYNC
AUDATA [3:0]
Start of execution at branch destination address in PC (1)
Start of execution at branch destination address in PC (2)
Figure 17.3 Example of Output in Case of Successive Branches



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