SH7052 datasheet(92/919 Pages) RENESAS

92 / 919 page

Power-On Reset Initiated by WDT: When a setting is made for a power-on reset to be generated

in the WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the chip enters the power-

on reset state.

The pin function controller (PFC) registers and I/O port registers are not initialized by the reset

signal generated by the WDT (these registers are only initialized by a power-on reset from off-

chip).

If reset caused by the input signal at the

RES pin and a reset caused by WDT overflow occur

simultaneously, the

RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.

When WDT-initiated power-on reset processing is started, the CPU operates as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception processing vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of

the status register (SR) are set to H'F (1111).

4. The values fetched from the exception processing vector table are set in the PC and SP, and the

program begins executing.

5.2.3

Manual Reset

When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode,

and the WDT’s TCNT overflows, the chip enters the power-on reset state.

When WDT-initiated manual reset processing is started, the CPU operates as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception processing vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of

the status register (SR) are set to H'F (1111).

4. The values fetched from the exception processing vector table are set in the PC and SP, and the

program begins executing.

In a manual reset the bus cycle is retained, but if a manual reset occurs while the bus is released or

during DMAC burst transfer, manual reset exception processing will be deferred until the CPU

acquires the bus. However, if the interval from generation of the manual reset until the end of the

bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal

manual reset source is ignored instead of being deferred, and manual reset exception processing is

not executed.

SH7052 bảng dữ liệu(PDF) 92 Page - Renesas Technology Corp