SH7052 datasheet(12/919 Pages) RENESAS

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Section 5

Exception Processing .................................................................................... 61

5.1

Overview............................................................................................................................

5.1.1

Types of Exception Processing and Priority ........................................................

5.1.2

Exception Processing Operations .........................................................................

5.1.3

Exception Processing Vector Table......................................................................

5.2

Resets.................................................................................................................................

5.2.1

Types of Reset ......................................................................................................

5.2.2

Power-On Reset....................................................................................................

5.2.3

Manual Reset........................................................................................................

5.3

Address Errors ...................................................................................................................

5.3.1

Address Error Sources..........................................................................................

5.3.2

Address Error Exception Processing....................................................................

5.4

Interrupts............................................................................................................................

5.4.1

Interrupt Sources ..................................................................................................

5.4.2

Interrupt Priority Level.........................................................................................

5.4.3

Interrupt Exception Processing ............................................................................

5.5

Exceptions Triggered by Instructions................................................................................

5.5.1

Types of Exceptions Triggered by Instructions....................................................

5.5.2

Trap Instructions ..................................................................................................

5.5.3

Illegal Slot Instructions ........................................................................................

5.5.4

General Illegal Instructions ..................................................................................

5.6

When Exception Sources Are Not Accepted.....................................................................

5.7

Stack Status after Exception Processing Ends...................................................................

5.8

Usage Notes .......................................................................................................................

5.8.1

Value of Stack Pointer (SP)..................................................................................

5.8.2

Value of Vector Base Register (VBR) .................................................................

5.8.3

Address Errors Caused by Stacking of Address Error Exception Processing......

Section 6

Interrupt Controller (INTC)......................................................................... 75

6.1

Overview............................................................................................................................

6.1.1

Features ................................................................................................................

6.1.2

Block Diagram......................................................................................................

6.1.3

Pin Configuration .................................................................................................

6.1.4

6.2

Interrupt Sources................................................................................................................

6.2.1

NMI Interrupts......................................................................................................

6.2.2

User Break Interrupt .............................................................................................

6.2.3

IRQ Interrupts ......................................................................................................

6.2.4

On-Chip Peripheral Module Interrupts ................................................................

6.2.5

Interrupt Exception Vectors and Priority Rankings .............................................

6.3

Description of Registers ....................................................................................................88

6.3.1

Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL) .............................

6.3.2

Interrupt Control Register (ICR) ..........................................................................

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