SH7052 datasheet(624/919 Pages) RENESAS

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17.4.3

Operation

Operation starts in RAM monitor mode AUDMD is driven high after

AUDRST has been asserted,

then

AUDRST is negated.

Figure 17.5 shows an example of a read operation, and figure 17.6 an example of a write

operation.

When

AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,

or data (writing only) is input in the format shown in figure 17.4 AUDATA Input Format,

execution of read/write access to the specified address is started. During internal execution, the

AUD returns Not Ready (0000). When execution is completed, the Ready flag (0001) is returned

(figures 17.5 and 17.6).

In a read, data of the specified size is output when

AUDSYNC is negated following detection of

this flag (figure 17.5).

If a command other than the above is input in DIR, the AUD treats this as a command error,

disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the

command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the

Ready flag to 1 (figure 17.7).

Table 17.2

Ready Flag Format

Bit 3

Bit 2

Bit 1

Bit 0

Fixed at 0

0: Normal status

1: Bus error

0: Normal status

1: Bus error

0: Not ready

1: Ready

Bus error conditions

1. Word access to address 4n+1 or 4n+3

2. Longword access to address 4n+1, 4n+2, or 4n+3

3. Longword access to on-chip I/O 8-bit space

4. Access to external space in single-chip mode

AUDCK

Not ready

DIR

Ready

Ready Ready

0001

0000

1000

0001

A31–A28

D7–D4

D3–D0

A3–A0

AUDSYNC

AUDATAn

Input/output switchover

Input

Output

Figure 17.5 Example of Read Operation (Byte Read)

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